1. Field of the Invention
The present invention relates to a power semiconductor device. More specifically, the present invention relates to a power semiconductor device having a lateral diffused MOS (LDMOS), which may be characterized as a high-power MOS, and a poly-silicon/insulator/poly-silicon (PIP) capacitor, and a method for manufacturing the same.
2. Description of the Related Art
Ideally, it is preferred for a power semiconductor device to be able to operate at a high voltage, close to a theoretical breakdown voltage of a semiconductor device. Accordingly, when an external system using a high voltage is controlled by an integrated circuit (IC), the IC needs elements for controlling the high voltage, and such elements must have a high breakdown voltage.
For example, in a drain or a source of a transistor directly receiving a high voltage, a punch through voltage between the drain/source and a semiconductor substrate and a breakdown voltage between the drain/source and a well of the semiconductor substrate must be higher than the high voltage received at the drain/source.
From among high-power semiconductor devices, an LDMOS transistor, which may be characterized as a high-power MOS transistor, has a structure suitable for operation at a high voltage because a channel region and a drain electrode are separated from each other about a drift region such that a gate electrode can control the channel region and the drain electrode.
Meanwhile, many analog circuits (e.g., manufactured using CMOS logic processes and CMOS semiconductor devices) may employ PIP and/or MIM capacitors. Since such capacitors are independent from bias, and may operate differently from a MOS-type capacitor or a junction capacitor, the PIP and MIM capacitors benefit from precision. Among the capacitors, the PIP capacitor is widely used for noise prevention and frequency modulation. With the development of a high integration technology for making semiconductor devices, the PIP capacitor can be integrated together with an LDMOS transistor.
Hereinafter, a structure of a conventional power semiconductor device having a PIP capacitor and an LDMOS transistor will be described with reference to accompanying drawings.
FIGS. 1A to 1C are sectional views showing a conventional method for manufacturing a power semiconductor device having a PIP capacitor and an LDMOS transistor.
Hereinafter, the conventional method for manufacturing the power semiconductor device having the PIP capacitor and the LDMOS transistor will be given.
As shown in FIG. 1A, a P type semiconductor substrate 10 includes an LDMOS transistor region A and a PIP capacitor region B.
In the semiconductor substrate 10 having the PIP capacitor region B and the LDMOS transistor region A, an N doped buried layer 11 is formed in the LDMOS transistor region A of the semiconductor substrate 10, a first P doped well 12 is formed in the buried layer 11, a field insulating layer 17 is formed on the surface of the first well 12 of the semiconductor substrate 10, a second P doped well 13 is formed in the first well 12 at one side of the field insulating layer 17, and a first P+ doping region 14 is formed on the surface of the second well 13. Thereafter, an N+ doped source region 15 is formed in a predetermined region of the first well 12 adjacent to the first doping region 14 and an N+ doped drain region 16 is formed in a predetermined region of the first well 12 spaced apart from the first doping region 14, respectively. The source region 15 and the drain region 16 are formed at both sides of the field insulating layer 17, respectively, while being separated from each other.
At this time, the field insulating layer 17 is also formed on the PIP capacitor region B during the process of forming the field insulating layer 17 on the LDMOS transistor region A.
A gate insulating layer 18 is formed on the entire surface of the substrate 10 when the field insulating layer 17 is formed, or shortly thereafter.
Then, a first poly-silicon layer 19 is deposited on the entire surface of the substrate 10 having the above structure.
Next, as shown in FIG. 1B, the first poly-silicon layer 19 is etched through a photolithography process, thereby forming a gate electrode 19a on the LDMOS transistor region A while forming a lower electrode 19B on the PIP capacitor region B.
Thereafter, as shown in FIG. 1C, after depositing an insulating layer on the entire surface of the substrate 10, an anisotropic etching process is performed, thereby forming sidewall spacers 20 at opposite sides of the gate electrode 19a and opposite sides of the lower electrode 19b. 
Then, a dielectric layer and a second poly-silicon layer are deposited on the entire surface of the resultant structure, and then a capacitor dielectric layer 22 and an upper electrode 24 are formed only on the PIP capacitor region B through a photolithography process.
Meanwhile, in FIG. 1C, “L” of the transistor region represents the width of the field insulating layer 17, and “HP” (half pitch) represents a distance between the source region 15 and the drain region 16.
In addition, it is necessary for the gate electrode 19a to enhance a breakdown voltage by lowering a strong electric field at a gate edge and to lower Ron and Rsp of the LDMOS transistor by reducing resistance of the first well 12.
In order to enhance the breakdown voltage of the LDMOS transistor, there has been suggested a method for increasing the value of the “L”. However, if the value of the “L” is increased, the value of the HP is also increased, so that the strength of the electric field may increase at the gate edge. Thus, the probability of the breakdown on the surface of the substrate may rise, and the Ron and Rsp may increase.